1. Field of the Invention
The present invention relates to an improvement in a mechanism which controls data coherence in a second buffer memory which is shared by a plurality of first buffer memories or cache memories.
2. Description of the Prior Art
In a second buffer memory shared by a plurality of first buffer memories of a store-through type, each time any one of the processors issues a store request, coherence control is performed with respect to the first buffer memories other than the first buffer memory connected to the processor which issued the store request. In coherence control, a block including an address of the store request is eliminated to prevent the inconsistency among the first buffer memories. The first buffer memories cannot receive the next request during coherence control. Therefore, during coherence control, it is necessary to prevent the processors themselves from having access to a buffer memory system.
In a conventional buffer memory system of the above type, the frequency of coherence control requests which are issued to the first buffer memories is increased, because the number of processors sharing a single main storage is increased. For this reason, on the one hand, the frequency of stopping the processors is increased, so there arises the problem that the overall performance of the system is reduced. Therefore, in order to enhance the overall performance of the system by increasing the number of processors, it is necessary to reduce the frequency of coherence control requests. On the other hand, in the conventional buffer memory system, coherence control is issued to all of the first buffer memories independently of whether each buffer memory includes a block with respect to which coherence control is performed.
A coherence control method for cache memories in a multiple processor system is disclosed in U.S. Pat. No. 5,265,232. In the method, a cross-invalid (XI) directory is provided on the side of a second cache memory, and each entry of the XI directory has a processor identifier (CPID) field for identifying an owner of that entry and an ownership field representative of the status of the ownership. In this prior art, the concept of "ownership" and the processor identifier field are combined so that invalidation can be realized by only changing the ownership identified by the processor identifier field.
However, in the above-described prior art, the ownership must be controlled by exclusive fetching, read-only fetching, conditionally-public fetching, and so on, so there is the drawback that ownership control becomes complicated.